
`include "common_header.verilog"

//  *************************************************************************
//  File : mac_control_xl
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited. 
//  Copyright (c) 2014 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Daniel Koehler
//  info@morethanip.com
//  *************************************************************************
//  Description : Configuration and Statistic Control Top Level for MAC
//  Version     : $Id: mac_control_xl.v,v 1.11 2017/07/06 15:13:26 gc Exp $
//  *************************************************************************

module mac_control_xl (

`ifdef MTIP_SDPM_GEN_GLOBAL_RST
   sdpm_core_reset,
   sdpm_bist_i,
   sdpm_bist_o,
`endif
   reset_rxclk,
   reset_txclk,
   reset_ff_tx_clk,
   reset_ff_rx_clk,
   ff_tx_clk,
   ff_rx_clk,
   rxclk,
   rxclk_ena,
   txclk,
   txclk_ena,
   reset_reg_clk,
   reg_clk,
   cs,
   rd,
   wr,
   sel,
   data_in,
   data_out,
   busy,
   rx_section_empty,
   rx_section_full,
   tx_section_empty,
   tx_section_full,
   loc_fault,
   rem_fault,
   li_fault,
   tx_isidle,
   tx_empty_st,
   rx_empty_st,
   phy_los,
   mac_mode,
   tx_ipg_length,
   tx_ipg_comp_cnt,
   mac_addr,
   tx_addr_ins,
   tx_pad_en,
   promis_en,
   frm_length_max,
   pad_en,
   crc_fwd,
   pause_fwd,
   rx_pause_bypass,
   pause_ignore,
   cmd_frm_ena,
   force_send_idle,
   rx_err_frm_disc,
   rx_short_disc,
   enable_tx,
   enable_rx,
   loop_ena,
   phy_txena,
   no_lgth_check,
   col_cnt_ext,
   sfd_any,
   tx_flush,
   xgmii_mode,
   lowp_ena,
   reg_lowp_int,
   reg_lowp,
   pfc_mode,
   pause_pfc_cmptbl,
   disable_flt_hdl,
   cl_pause_quanta,
   cl_pause_thresh,
   qmodeidle8x,
`ifdef MTIPM10_SWRST_CMPTBL
   rx_sw_reset,
   rx_sw_reset_done,
   tx_sw_reset,
   tx_sw_reset_done,
`else
   rx_credit_max,
   rx_credit_reset,
   rx_credit_reset_done,
   rx_credit,
`endif
   sw_reset,
   tx_pause_on,
   tx_ts_val,
   tx_ts_frm_out,
   tx_ts,
   reg_ts_avail,
`ifdef MTIPMAC_1SIF
   os_enable,
`endif
   hash_tab,
`ifdef MTIP_DIR_CONFIG
   mode_set_wr,
   set_1g_mode,
`endif
   if_mode_set,
   if_mode_ena,
   mii_ena_10,
   mgmii_ena_r,
   mii_ena_r,
   mgmii_ena_t,
   mii_ena_t,
   mdc,
   mdio_in,
   mdio_out,
   mdio_oen
`ifdef MTIPMAC_XSTAT
   ,
   tx_mtu
`endif
`ifndef MTIPMAC_XSTAT
   ,
   rsv_stat_val,
   rsv_stat,
   rsv_stat_pfc,
   frm_align_err,
   tsv_stat_val,
   tsv_stat,
   tsv_stat_pfc
  `ifdef MTIPSTAT_MEM_EXTERNAL
   ,
   rstm_raddr,
   rstm_rden,
   rstm_rdata,
   rstm_wren,
   rstm_waddr,
   rstm_wdata,
   tstm_raddr,
   tstm_rden,
   tstm_rdata,
   tstm_wren,
   tstm_waddr,
   tstm_wdata
  `endif
`endif
   );

`include "mtip_40geth_pack_package.verilog"

`ifdef MTIP_SDPM_GEN_GLOBAL_RST
input   sdpm_core_reset;        // global memory reset for special memories
input   [`MTIP_SDPM_GEN_BIST_I:0] sdpm_bist_i;  // inputs to ALL memories but not necessarily all used in this instance.
output  [`MTIP_SDPM_GEN_BIST_O:0] sdpm_bist_o;  // outputs OR'ed from ALL memories when travelling up the hierarchies
`endif
input   reset_rxclk;                            //  Asynchronous Reset - rx_clk Domain
input   reset_txclk;                            //  Asynchronous Reset - tx_clk Domain
input   reset_ff_tx_clk;                        //  Asynchronous Reset - ff_tx_clk Domain
input   reset_ff_rx_clk;                        //  Asynchronous Reset - ff_rx_clk Domain
input   ff_tx_clk;                              //  Transmit Local Clock        
input   ff_rx_clk;                              //  Receive Local Clock
input   rxclk;                                  //  XGMII Receive Clock
input   rxclk_ena;                              //  XGMII Receive Clock Enable
input   txclk;                                  //  XGMII Transmit Clock
input   txclk_ena;                              //  XGMII Transmit Clock Enable
input   reset_reg_clk;                          //  Asynchronous Reset - reg_clk Domain
input   reg_clk;                                //  ReferenceInterface Clock
input   cs;                                     //  Chip Select
input   rd;                                     //  Register Read Strobe
input   wr;                                     //  Register Write Strobe
input   [7:0] sel;                              //  Register Address
input   [31:0] data_in;                         //  Write Data for Host Bus
output  [31:0] data_out;                        //  Read Data to Host Bus
output  busy;                                   //  Interface Busy
output  [ING_ADDR - 1:0] rx_section_empty;      //  Receive Section Empty - Pause Frame Generation Threshold 
output  [ING_ADDR - 1:0] rx_section_full;       //  Receive Section Full - FIFO Status 
output  [EG_ADDR - 1:0] tx_section_empty;       //  Transmit Section Empty - FIFO Status
output  [EG_ADDR - 1:0] tx_section_full;        //  Transmit Section Full - MAC Tx Start           
input   loc_fault;                              //  RX receives LF sequences
input   rem_fault;                              //  RX receives RF sequences        
input   li_fault;                               //  RX receives LinkInterruption sequences
input   tx_isidle;                              //  Transmit Statemachine is in IDLE
input   tx_empty_st;                            //  TX FIFO empty (data+status)
input   rx_empty_st;                            //  RX FIFO empty (data+status)
input   phy_los;                                //  PHY Loss of Signal Indication
output  mac_mode;                               //  WAN mode
output  [6:0] tx_ipg_length;                    //  WAN/LAN mode IPG setting. STANDARD=12 (for both modes)
output  [15:0] tx_ipg_comp_cnt;                 //  IPG compensation count
output  [47:0] mac_addr;                        //  Device Ethernet MAC address
output  tx_addr_ins;                            //  Insert MAC Source Address
output  tx_pad_en;                              //  Transmit Padding Enable
output  promis_en;                              //  Enable promiscuous mode: accept any frame 
output  [15:0] frm_length_max;                  //  Maximum Received Frame length                
output  pad_en;                                 //  Enable Padding
output  crc_fwd;                                //  Forward Frames with CRC to Application
output  pause_fwd;                              //  Forward Pause Frames to Application
output  rx_pause_bypass;                        //  if 1 the pause frame removal datapath function is bypassed 
output  pause_ignore;                           //  Ignore Pause Frames Quantas
output  cmd_frm_ena;                            //  Enable Command Frames
output  force_send_idle;                        //  force Idle send
output  rx_err_frm_disc;                        //  Discard Received Errored Frames
output  rx_short_disc;                          //  Discard Received short frames (within FIFO)
output  enable_tx;                              //  Enable Tx Path         
output  enable_rx;                              //  Enable Rx Path
output  loop_ena;                               //  PHY Loopback Enable
output  phy_txena;                              //  PHY Transmit Enable
output  no_lgth_check;                          //  Disable Length Field Check 
output  col_cnt_ext;                            //  Extend COL_CNT in Link Fault SM
output  sfd_any;                                //  allow any SFD character
output  tx_flush;                               //  Flush egress pipeline
output  xgmii_mode;                             //  XGMII mode enable (0=XLGMII, 1=XGMII)
output  lowp_ena;                               //  Enable Low Power Idle Generation
input   reg_lowp_int;                           //  Low Power Indication from MAC - local (rx_clk)
output  reg_lowp;                               //  Low Power Indication out to toplevel (reg_clk)
output  pfc_mode;                               //  Priority Flow Control (Class Based Pause) enable
output  pause_pfc_cmptbl;                       //  Link Pause Compatibility with PFC mode enable
output  disable_flt_hdl;                        //  if '1', RX RS does not affect TX data path
output  [8 * 16 - 1:0] cl_pause_quanta;         //  Class 0..7 PFC Quanta value
output  [8 * 16 - 1:0] cl_pause_thresh;         //  Threshold for Class 0..7 Refresh PFC Frame
output  qmodeidle8x;                            //  consider clock-enable during IDLE to be 8x faster (i.e. byte clock instead word clock)
`ifdef MTIPM10_SWRST_CMPTBL
output  rx_sw_reset;                            //  FIFO sync reset (ff_rx_clk)
input   rx_sw_reset_done;                       //  FIFO reset completed, pulse (ff_rx_clk)
output  tx_sw_reset;                            //  FIFO sync reset (ff_tx_clk)
input   tx_sw_reset_done;                       //  FIFO reset completed, pulse (ff_tx_clk)
`else
output  [7:0] rx_credit_max;                    //  credit counter init/max value (ff_rx_clk)
output  rx_credit_reset;                        //  FIFO reset (ff_rx_clk)
input   rx_credit_reset_done;                   //  FIFO reset completed, pulse (ff_rx_clk)
input   [7:0] rx_credit;                        //  current credit counter value (ff_rx_clk)
`endif
output  sw_reset;                               //  sync reset pulse (reg_clk)
input   [7:0] tx_pause_on;                      //  per class pause condition
input   tx_ts_val;                              //  timestamp valid
input   tx_ts_frm_out;                          //  store timestamp
input   [31:0] tx_ts;                           //  transmit timestamp
output  reg_ts_avail;                           //  ts_avail status bit
`ifdef MTIPMAC_1SIF
output  os_enable;                              //  enable 1-step datapath functions (reg_clk)
`endif
output  [63:0] hash_tab;                        //  Hash table
`ifdef MTIP_DIR_CONFIG
input   mode_set_wr;                            // one reg_clk clock pulse to write the mode settings
input   set_1g_mode;                            // Value to be written in the bit MAC_IF_MODE[1]
`endif
input   [1:0] if_mode_set;                      //  Interface selection from extern control (async)
output  [1:0] if_mode_ena;                      //  Current Interface selection indication
output  mii_ena_10;                             //  indicate 10Mbps for MII (control to RMII)
output  mgmii_ena_r;                            //  interface mode to use MII/GMII (1) or XGMII (0), rxclk domain
output  mii_ena_r;                              //  interface mode to use MII (1) or GMII (0), rxclk domain
output  mgmii_ena_t;                            //  interface mode to use MII/GMII (1) or XGMII (0), txclk domain
output  mii_ena_t;                              //  interface mode to use MII (1) or GMII (0), txclk domain
output  mdc;                                    //   2.5MHz Interface                    
input   mdio_in;                                //   Data Bus In                         
output  mdio_out;                               //   Data Bus Out                        
output  mdio_oen;                               //   Data Bus Output Enable              

`ifdef MTIPMAC_XSTAT
output  [15:0] tx_mtu;          //  Maximum Frame length for TX (statistics)
`endif

`ifndef MTIPMAC_XSTAT
input   rsv_stat_val;                           //  Receive Statistic Vector Valid.
input   [31:0] rsv_stat;                        //  Receive Statistic Vector.
input   [7:0] rsv_stat_pfc;                     //  pfc class bits from received PFC frame
input   frm_align_err;                          //  Received Frame Aligment Error Indication
input   tsv_stat_val;                           //  Transmit Statistic Vector Valid.
input   [24:0] tsv_stat;                        //  Transmit Statistic Vector.
input   [7:0] tsv_stat_pfc;                     //  the class enable of latest generated frame

 `ifdef MTIPSTAT_MEM_EXTERNAL

 output [STAT_CNT_ADDR-1:0] rstm_raddr;                         // Stats RX mem Read address (rxclk)
 output rstm_rden;                                              // Stats RX mem read enable (rxclk)
 input  [STAT_CNT_WIDTH+STAT_CNT_SATURATE-1:0] rstm_rdata;      // Stats RX mem Read data (rxclk)
 output rstm_wren;                                              // Stats RX mem write (rxclk)
 output [STAT_CNT_ADDR-1:0] rstm_waddr;                         // Stats RX mem write address (rxclk)
 output [STAT_CNT_WIDTH+STAT_CNT_SATURATE-1:0] rstm_wdata;      // Stats RX mem write data (rxclk)

 output [STAT_CNT_ADDR-1:0] tstm_raddr;                         // Stats TX mem Read address (txclk)
 output tstm_rden;                                              // Stats TX mem read enable (txclk)
 input  [STAT_CNT_WIDTH+STAT_CNT_SATURATE-1:0] tstm_rdata;      // Stats TX mem Read data (txclk)
 output tstm_wren;                                              // Stats TX mem write (txclk)
 output [STAT_CNT_ADDR-1:0] tstm_waddr;                         // Stats TX mem write address (txclk)
 output [STAT_CNT_WIDTH+STAT_CNT_SATURATE-1:0] tstm_wdata;      // Stats TX mem write data (txclk)

 wire   [STAT_CNT_ADDR-1:0] rstm_raddr;
 wire   rstm_rden; 
 wire   rstm_wren; 
 wire   [STAT_CNT_ADDR-1:0] rstm_waddr;
 wire   [STAT_CNT_WIDTH+STAT_CNT_SATURATE-1:0] rstm_wdata;

 wire   [STAT_CNT_ADDR-1:0] tstm_raddr;
 wire   tstm_rden; 
 wire   tstm_wren; 
 wire   [STAT_CNT_ADDR-1:0]   tstm_waddr;
 wire   [STAT_CNT_WIDTH+STAT_CNT_SATURATE-1:0] tstm_wdata;

 `endif

`endif

wire    [31:0] data_out; 
wire    busy; 
wire    [ING_ADDR - 1:0] rx_section_empty; 
wire    [ING_ADDR - 1:0] rx_section_full; 
wire    [EG_ADDR - 1:0] tx_section_empty; 
wire    [EG_ADDR - 1:0] tx_section_full; 
wire    mac_mode; 
wire    [6:0] tx_ipg_length; 
wire    [15:0] tx_ipg_comp_cnt;
wire    [47:0] mac_addr; 
wire    tx_addr_ins; 
wire    tx_pad_en; 
wire    promis_en; 
wire    [15:0] frm_length_max; 
wire    pad_en; 
wire    crc_fwd; 
wire    pause_fwd;
wire    rx_pause_bypass; 
wire    pause_ignore; 
wire    cmd_frm_ena; 
wire    force_send_idle; 
wire    rx_err_frm_disc; 
wire    rx_short_disc;
wire    enable_tx; 
wire    enable_rx; 
wire    loop_ena; 
wire    phy_txena; 
wire    no_lgth_check; 
wire    col_cnt_ext; 
wire    sfd_any; 
wire    tx_flush; 
wire    xgmii_mode;
wire    lowp_ena; 
wire    pfc_mode; 
wire    pause_pfc_cmptbl; 
wire    disable_flt_hdl;
wire    [8 * 16 - 1:0] cl_pause_quanta; 
wire    [8 * 16 - 1:0] cl_pause_thresh; 
wire    qmodeidle8x;
`ifdef MTIPM10_SWRST_CMPTBL
wire    rx_sw_reset;
wire    tx_sw_reset;
`else
wire    [7:0] rx_credit_max; 
wire    rx_credit_reset; 
`endif
wire    sw_reset; 
wire    reg_ts_avail; 
`ifdef MTIPMAC_1SIF
wire    os_enable;
`endif
wire    [63:0] hash_tab; 
wire    [1:0] if_mode_ena; 
wire    mii_ena_10; 
wire    mgmii_ena_r; 
wire    mii_ena_r; 
wire    mgmii_ena_t; 
wire    mii_ena_t; 
wire    mdc; 
wire    mdio_out; 
wire    mdio_oen; 
`ifdef MTIPMAC_XSTAT
wire    [15:0] tx_mtu;          //  Maximum Frame length for TX (statistics)
`endif

wire    reg_rd;                 //  Register Read Strobe
wire    reg_wr;                 //  Register Write Strobe
wire    [7:0] reg_sel;          //  Register Address
wire    [31:0] reg_data_in;     //  Write Data from Host Bus
wire    [31:0] reg_data_out;    //  Read Data to Host Bus
wire    stat_rd;                //  Statistics registers access
wire    stat_busy;              //  Statistics Counter read busy
wire    rst_status;             //  Reset Status Register
wire    sw_reset_int;           //  sync reset pulse (reg_clk)
wire    [15:0] frm_length_max_int; //  Maximum Received Frame length                
wire    [15:0] tx_mtu_int;      //  Maximum Frame length for TX (statistics)
//  MDIO Interface
//  --------------
wire    [15:0] mdio_data_out;   //  Data from MDIO module
wire    mdio_busy_trans;        //  ongoing MDIO transaction indication
wire    mdio_rd;                //  Read Enable
wire    mdio_wr;                //  Write Enable
wire    mdio_busy;              //  Local register R/W transaction                                 

//  MII/GMII/XGMII RS Control
//  ---------
wire    sg_rd;                  //  register read
wire    sg_wr;                  //  register write
wire    [15:0] sgpcs_data_out;  //  read data from SGMII PCS module
wire    mgmii_ena;              //  interface mode to use MII/GMII (1) or XGMII (0)
wire    mii_ena;                //  interface mode to use MII (1) or GMII (0)

//  statistics module
//  -----------------
wire    [31:0] stat_data_out; 

//  wire locals to top
//  ------------------
assign sw_reset = sw_reset_int; 
assign frm_length_max = frm_length_max_int; 

`ifdef MTIPMAC_XSTAT
assign tx_mtu = tx_mtu_int;
`endif

//  Host interface Control
//  ----------------------
host_control_xl U_HCTL (
          .reset(reset_reg_clk),
          .clk(reg_clk),
          .cs(cs),
          .rd(rd),
          .wr(wr),
          .sel(sel),
          .data_in(data_in),
          .data_out(data_out),
          .busy(busy),
          .reg_rd(reg_rd),
          .reg_wr(reg_wr),
          .reg_sel(reg_sel),
          .reg_data_in(reg_data_in),
          .reg_data_out(reg_data_out),
          .mdio_rd(mdio_rd),
          .mdio_wr(mdio_wr),
          .mdio_busy(mdio_busy),
          .stat_rd(stat_rd),
          .stat_busy(stat_busy),
          .rst_status(rst_status));

register_map_xl #(
        // use instance parameters instead package parameters
          .EG_FIFO(EG_FIFO)  , .EG_ADDR(EG_ADDR),       // TX FIFO size
          .ING_FIFO(ING_FIFO), .ING_ADDR(ING_ADDR))     // RX FIFO size
U_REG (
          .reset_rxclk(reset_rxclk),
          .reset_txclk(reset_txclk),
          .reset_ff_tx_clk(reset_ff_tx_clk),
          .reset_ff_rx_clk(reset_ff_rx_clk),
          .ff_tx_clk(ff_tx_clk),
          .ff_rx_clk(ff_rx_clk),
          .reset_reg_clk(reset_reg_clk),
          .rxclk(rxclk),
          .rxclk_ena(rxclk_ena),
          .txclk(txclk),
          .txclk_ena(txclk_ena),
          .reg_clk(reg_clk),
          .reg_rd(reg_rd),
          .reg_wr(reg_wr),
          .reg_sel(reg_sel),
          .reg_data_in(reg_data_in),
          .reg_data_out(reg_data_out),
          .rst_status(rst_status),
          .rx_section_empty(rx_section_empty),
          .rx_section_full(rx_section_full),
          .tx_section_empty(tx_section_empty),
          .tx_section_full(tx_section_full),
          .loc_fault(loc_fault),
          .rem_fault(rem_fault),
          .li_fault(li_fault),
          .tx_isidle(tx_isidle),
          .tx_empty_st(tx_empty_st),
          .rx_empty_st(rx_empty_st),
          .phy_los(phy_los),
          .mac_mode(mac_mode),
          .tx_ipg_length(tx_ipg_length),
          .tx_ipg_comp_cnt(tx_ipg_comp_cnt),
          .mac_addr(mac_addr),
          .tx_addr_ins(tx_addr_ins),
          .tx_pad_en(tx_pad_en),
          .promis_en(promis_en),
          .frm_length_max(frm_length_max_int), //  local
          .tx_mtu(tx_mtu_int), //  local
          .pad_en(pad_en),
          .crc_fwd(crc_fwd),
          .pause_fwd(pause_fwd),
          .rx_pause_bypass(rx_pause_bypass),
          .pause_ignore(pause_ignore),
          .cmd_frm_ena(cmd_frm_ena),
          .force_send_idle(force_send_idle),
          .rx_err_frm_disc(rx_err_frm_disc),
          .rx_short_disc(rx_short_disc),
          .enable_tx(enable_tx),
          .enable_rx(enable_rx),
          .loop_ena(loop_ena),
          .phy_txena(phy_txena),
          .no_lgth_check(no_lgth_check),
          .col_cnt_ext(col_cnt_ext),
          .sfd_any(sfd_any),
          .tx_flush(tx_flush),
          .xgmii_mode(xgmii_mode),
          .lowp_ena(lowp_ena),
          .reg_lowp_int(reg_lowp_int),
          .reg_lowp(reg_lowp),
          .pfc_mode(pfc_mode),
          .pause_pfc_cmptbl(pause_pfc_cmptbl),
          .disable_flt_hdl(disable_flt_hdl),
          .cl_pause_quanta(cl_pause_quanta),
          .cl_pause_thresh(cl_pause_thresh),
          .qmodeidle8x(qmodeidle8x),
      `ifdef MTIPM10_SWRST_CMPTBL
          .rx_sw_reset(rx_sw_reset),
          .rx_sw_reset_done(rx_sw_reset_done),
          .tx_sw_reset(tx_sw_reset),
          .tx_sw_reset_done(tx_sw_reset_done),
      `else
          .rx_credit_max(rx_credit_max),
          .rx_credit_reset(rx_credit_reset),
          .rx_credit_reset_done(rx_credit_reset_done),
          .rx_credit(rx_credit),
      `endif
          .sw_reset(sw_reset_int), //  local
          .tx_pause_on(tx_pause_on),
          .tx_ts_val(tx_ts_val),
          .tx_ts_frm_out(tx_ts_frm_out),
          .tx_ts(tx_ts),
          .reg_ts_avail(reg_ts_avail),
      `ifdef MTIPMAC_1SIF
          .os_enable(os_enable),
      `endif
          .hash_tab(hash_tab),
          .mdio_data_out(mdio_data_out),
          .mdio_busy_trans(mdio_busy_trans),
          .sgpcs_data_out(sgpcs_data_out),
          .stat_data_out(stat_data_out));

top_mdio_xl #(.MDIO_CLK_DIV(MDIO_CLK_DIV)) U_MDIO (
          .reset(reset_reg_clk),
          .clk(reg_clk),
          .mdc(mdc),
          .mdio_in(mdio_in),
          .mdio_out(mdio_out),
          .mdio_oen(mdio_oen),
          .mdio_data_in(reg_data_in[15:0]),
          .mdio_data_out(mdio_data_out),
          .mdio_busy_trans(mdio_busy_trans),
          .mdio_addr(reg_sel[1:0]),
          .mdio_rd(mdio_rd),
          .mdio_wr(mdio_wr),
          .mdio_busy(mdio_busy));

//  MII/GMII/XGMII RS Registers
//  --------------------
assign sg_rd = reg_rd & reg_sel[7] & reg_sel[6]; //  0xc0 and above
assign sg_wr = reg_wr & reg_sel[7] & reg_sel[6]; //  0xc0 and above

register_map_mgmii U_RSREG (
          .reset_reg_clk(reset_reg_clk),
          .reg_clk(reg_clk),
          .reg_rd(sg_rd),
          .reg_wr(sg_wr),
          .reg_sel(reg_sel[3:0]),
          .reg_data_in(reg_data_in[15:0]),
          .reg_data_out(sgpcs_data_out),
        `ifdef MTIP_DIR_CONFIG
          .mode_set_wr(mode_set_wr),
          .set_1g_mode(set_1g_mode),
        `endif
          .if_mode_set(if_mode_set),
          .if_mode_ena(if_mode_ena),
          .mii_ena_10(mii_ena_10),
          .mgmii_ena(mgmii_ena), //  local
          .mii_ena(mii_ena));

// synchronize enable signal to rx/tx clock domains
mtip_xsync #(2) U_SGENAR (
          .data_in({mgmii_ena, mii_ena}),
          .reset(reset_rxclk),
          .clk(rxclk),
          .data_s({mgmii_ena_r, mii_ena_r}));

mtip_xsync #(2) U_SGENAT (
          .data_in({mgmii_ena, mii_ena}),
          .reset(reset_txclk),
          .clk(txclk),
          .data_s({mgmii_ena_t, mii_ena_t}));

`ifdef MTIPMAC_XSTAT

//  No Statistics Module (Counters)
//  -------------------------------
assign stat_data_out = {32{1'b 0}}; //  local
assign stat_busy = ~reg_rd;      // avoid deadlock when reading stats

`else

`ifdef MTIPM10_STAT_CNT_HCK

        // ---------------------------------
        // read/modify/write RAM based Statistics operating in host clock domain (reg_clk)
        // ---------------------------------

  stats_hck_topn #( STAT_CNT_WIDTH,
                STAT_CNT_SATURATE) //  want to support saturation option (otherwise wrap only and stc_saturate has no effect)

        U_STAT (	
        
          .reset_rxclk(reset_rxclk),
          .reset_txclk(reset_txclk),
          .reset_reg_clk(reset_reg_clk),
          .rxclk(rxclk),
          .txclk(txclk),
          .reg_clk(reg_clk),
          .reg_rd(reg_rd),
          .reg_wr(reg_wr),
          .reg_sel(reg_sel),
          .reg_data_in(reg_data_in),
          .stat_data_out(stat_data_out),
          .stat_rd(stat_rd),
          .stat_busy(stat_busy),
          .sw_reset(sw_reset_int),
          .sw_reset_done(),
          .tx_mtu(tx_mtu_int),
        `ifdef STAT_PFCCNT_ENA
          .tsv_stat_pfc(tsv_stat_pfc),
          .rsv_stat_pfc(rsv_stat_pfc),
        `endif          
          .rsv_stat_val(rsv_stat_val),
          .rsv_stat(rsv_stat),
          .frm_align_err(frm_align_err),
          .tsv_stat_val(tsv_stat_val),
          .tsv_stat(tsv_stat));

`else

        // ---------------------------------
        // read/modify/write RAM based Statistics operating in line clock domains
        // ---------------------------------

  stats_topn_xl #( STAT_CNT_WIDTH,
                STAT_CNT_SATURATE) //  want to support saturation option (otherwise wrap only and stc_saturate has no effect)

        U_STAT (	

        `ifdef MTIP_SDPM_GEN_GLOBAL_RST
          .sdpm_core_reset(sdpm_core_reset),
          .sdpm_bist_i(sdpm_bist_i),
          .sdpm_bist_o(sdpm_bist_o),
        `endif        
          .reset_rxclk(reset_rxclk),
          .reset_txclk(reset_txclk),
          .reset_reg_clk(reset_reg_clk),
          .rxclk(rxclk),
          .txclk(txclk),
          .reg_clk(reg_clk),
          .reg_rd(reg_rd),
          .reg_wr(reg_wr),
          .reg_sel(reg_sel),
          .reg_data_in(reg_data_in),
          .stat_data_out(stat_data_out),
          .stat_rd(stat_rd),
          .stat_busy(stat_busy),
          .sw_reset(sw_reset_int),
          .sw_reset_done(),
          .tx_mtu(tx_mtu_int),
        `ifdef STAT_PFCCNT_ENA
          .tsv_stat_pfc(tsv_stat_pfc),
          .rsv_stat_pfc(rsv_stat_pfc),
        `endif          
          .rsv_stat_val(rsv_stat_val),
          .rsv_stat(rsv_stat),
          .frm_align_err(frm_align_err),
          .tsv_stat_val(tsv_stat_val),
          .tsv_stat(tsv_stat)
        `ifdef MTIPSTAT_MEM_EXTERNAL
          ,
          .rstm_raddr(rstm_raddr),
          .rstm_rden (rstm_rden ),
          .rstm_rdata(rstm_rdata),
          .rstm_wren (rstm_wren ),
          .rstm_waddr(rstm_waddr),
          .rstm_wdata(rstm_wdata),
          .tstm_raddr(tstm_raddr),
          .tstm_rden (tstm_rden ),
          .tstm_rdata(tstm_rdata),
          .tstm_wren (tstm_wren ),
          .tstm_waddr(tstm_waddr),
          .tstm_wdata(tstm_wdata)
        `endif
);

`endif

`endif   // MTIPMAC_XSTAT

endmodule // module mac_control_xl

